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blub000024 karma

Thanks for doing this. I have several questions:

  • Which do you prefer: VHDL or Verilog?
  • How much time is spent simulating the hardware vs. designing it (also do you use custom simulation software)?
  • how often do you actually have to go down to the gate-level to fix timing issues and other stuff?
  • Are all of the standard cells you use designed in-house?
  • How do you prefer to design your state machines (moore, mealy, latched mealy)?

Thanks for answering.